In contrast to traditional planar metal-oxide-semiconductor field-effect transistors (MOSFETs), which are fabricated using conventional lithographic fabrication methods, nonplanar FETs incorporate various vertical transistor structures, and typically include two or more gate structures formed in parallel. One such semiconductor structure is the “FinFET,” which takes its name from the multiple thin silicon “fins” that are used to form the respective gate channels, and which are typically on the order of tens of nanometers in width. The width of the gate in such transistors determines the effective channel length of the device.
Transistors with smaller channel lengths and smaller gate pitch exhibit higher current drive strength and less capacitance, and can operate at higher frequency, thus providing overall increased device performance. However, as semiconductor structures approach the 22 nanometer (nm) and 15 nm technology nodes, transistors with small channel lengths may suffer from static current leakage, with the static current leakage increasing as the channel length decreases. Further, processes for fabricating such small channel length transistors often result in high channel length variability, which can adversely affect transistor performance. While certain transistors in a semiconductor device may perform functions such as critical timing, and thus require short channel lengths, not all transistors of the structure will perform such functions. These transistors can be fabricated with wider channel lengths, thus overcoming leakage problems and fabrication variability. In addition it might be desirable to have N-channel and P-channel transistors of different channel lengths due to the difference in junction abruptness, charge carrier mobility, and gate electrode work function. Therefore, it is desirable to form semiconductor structures with gate structures of different widths. However, because of the very small tolerances involved, current methods for fabricating such structures are difficult.
One technique for creating various gate lengths on final lithographically printed and etched gates in a bulk or silicon-on-insulator (SOI) silicon wafer process is called pitch splitting. Pitch splitting is a technique that uses two masks to create a pitch that is half as big as the original. Half the data is put on one mask and the other half of the data is put on a second mask. The channel length scaling must be accomplished on each split pitch mask by adding a wider drawn channel length on selected devices during optical proximity correction (OPC). The two masks are each exposed to generate a composite photo image of the final pattern on a resist. The patterned resist is then used to etch the final pattern into the semiconductor wafer. This process is expensive due to the use of two masks. Also, since two masks are needed to produce the final image, the alignment tolerance between the two masks becomes an issue, which in turn affects the final design rules, resulting in less dense design rules. Further, with a two mask dual exposure, there is no guarantee that both exposures will be the same and will deliver the same nominal target for the minimum channel length devices or the channel length scaled devices.
In addition, since gate length scaling on traditional split pitch approaches is based on two OPC adjusted masks, the gate length scaled devices cannot be adjusted without affecting the minimum channel devices since they are exposed by the lithographic stepper simultaneously. Also, the optical proximity corrected masks themselves may have different critical dimensions (CDs) since they are generated separately. The combination of being generated separated and exposed separately may lead to bimodal distributions of channel lengths on every other transistor.
Conventional gate length scaling via pitch splitting is controlled by a schematic and graphic design system (GDS) based computer aided design (CAD) flow to describe which gates acquire the additional CD bias. For example, Blaze DFM provides a CAD based solution to effectively bias the gate length of individual gates. The Blaze DFM CAD flow involves schematic capture, netlisting, simulation, and mask data preparation to resize the gates on a mask to lithographically print wider or narrower gate lengths. The bias can be applied to one or more gates within the flow. A CAD recognition layer is drawn over the gate, and the mask is then modified during an OPC mask data preparation step. The schematic contains the gate sizing information for each gate. The amount of upsizing or downsizing is controlled by the CAD flow, and the data is sent to the mask shop showing the device coordinate and the amount of retargeting to be applied to each side of the gate. At this point, the gate resizing is fixed on the mask, and all devices are controlled by final resist exposure and etch. In the case of split pitch mask processing, this approach must be done on each corresponding split pitch mask for each gate. Accordingly, for every new product in which the gates are resized, new OPC mask data must be prepared and new masks created.
Another technique for creating various gate lengths is a sidewall image transfer (SIT) process. SIT based processing can be used for very regular patterns such as a grating pattern (a repeating pattern of lines all at the same pitch). SIT processing utilizes one photomask printed at twice the desired pitch to create mandrels. Then a spacer is formed on each side of each mandrel, the mandrels are removed, and the spacers left behind define two lines at the desired pitch (which is half of the original pitch). The SIT gate spacer process typically produces a non-lithographically defined, uniform gate length across the wafer, with the gate length being a function of the spacer bottom wall width. Since the spacer width and original mandrel pitch set the feature sizes of interest, no channel length scaling is possible with a simple SIT based flow.
Most often, short gate lengths at minimum spacing are required to support the typical logic gate layout and density. However, short gates have a greater variability in gate length and in the related transistor performance. Also, short gates have a high local variation, mismatch, and global variation of transistor parameters due to increased sensitivity to line edge roughness and dopant variation. In addition, whereas low power mobile platforms or battery backup systems are generally needed to reduce static current in order to lengthen battery operation times, channel length scaling would help reduce the static leakage on non critical timing paths. Channel length scaling could also be used on non critical timing paths to reduce total power. Memory bit cells often use extended gate lengths to provide better bit cell stability due to random dopant fluctuation in the channel and to reduce the effects of line edge roughness (LER).
A need therefore exists for methods which can produce multiple fine grained gate lengths on a single substrate using SIT processing with a corresponding CAD flow.